In the semiconductor industry, the use of relaxed SiGe layers as a template for strained Si layer growth has been the primary approach employed to create tensile-strained Si for possible use in high-performance complementary metal oxide semiconductor (CMOS) circuits. The strained Si layers provide improved charge carrier transportation compared to unstrained materials.
The viability of using such materials in mainstream CMOS applications will ultimately depend on manufacturing issues such as cost and circuit yield. Because most techniques for creating a relaxed SiGe layer involve plastically deforming an initially pseudomorphic strained Si film, residual dislocation defects tend to be present in all relaxed SiGe and strained Si materials. Thus, in addition to yield challenges inherent to any material change in CMOS processing, the additional challenge of defect-related yield issues will exist as well.
To minimize this challenge, many approaches have been created in an attempt to reduce the dislocation defect density in relaxed SiGe and strained Si layers. Dislocation defects are generally reported in the prior art as threading defects, which are single defect lines that pass through, i.e., thread, a material layer. The density of the threading defects is generally reported in the range from 105 to 108 threads/cm2. Due to their lower density and lack of any reliable defect etching techniques, there has essentially been no discussions or reports of planar defects (stacking faults or microtwins) in the literature.
Because typical densities of planar defects are below 106 defects/cm2, it becomes unlikely that even low magnification plan-view transmission electron microscopy (TEM) can detect these defects. Even if a very large prepared area was made and one planar defect was detected after 20 or so frames, it would tend to be discounted as anomalous.
A recent defect etch that was developed (see, U.S. application Ser. No. 10/654,231, filed Sep. 3, 2003, which has been incorporated herein by reference) to study strained Si and SiGe layers has shown that planar defects are far more ubiquitous than previously thought. Planar defects most likely represent a far more serious threat to device operation than an isolated threading dislocation because in contrast to a threading dislocation, a planar defect represents an entire plane of broken or distorted atomic bonds and therefore defects of this type affect a larger cross-sectional area of the crystal.
In view of the serious threat of planar defects, there is a need for developing a method to reduce stacking faults and other planar defects in strained Si/relaxed SiGe technologies.